The here disclosed technology relates to techniques for fabricating a 3D non-volatile memory device whose memory elements include an ONO or like charge storage structure.
Recently, ultra-high density storage devices have been proposed using three-dimensionally (3D) stacked memory structures. One example is referred to as a Bit Cost Scalable (BiCS) architecture. In one embodiment, a stacked and alternating array of conductive layers and dielectric layers is provided. A memory hole (MH) is formed by etching down through the layers to define a large number of memory layers simultaneously. A NAND connected string of memory elements is then formed by filling the sidewall and core of the memory hole with appropriate materials. A straight down NAND string may be formed by providing source and drain contacts at the top and bottom of the filled memory hole. Alternatively, a U-shaped or otherwise snaked NAND connected string of memory elements (P—BiCS) may be formed so as to includes adjacent pairs of memory holes, each having a vertical column of memory cells, where the strings are connected at their bottoms by way of a bottom-side back gate. Source and drain contacts are made at the top of the P—BiCS structure. Control gates of the respective memory cells are respectively provided by the stacked conductive layers. However, various challenges are presented in fabricating such memory devices.